Simco - Die Attach Equipment and ESD

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In semiconductor manufacturing, the die attach operation takes the singulated chips from the wafer and places them in a new target location (such as a tray, substrate, printed circuit board, etc.). Four general categories of ESD failure modes have been observed at this operation, namely: Charged Device Model (CDM), Field Induced Model (FIM), Machine Model (MM), and Charged Board Model (CBM). We have identified seven distinct mechanisms in typical die attach operations that can and do cause ESD damage to the chips being handled. They are reviewed here.

First, to hold semiconductor wafers in place and to facilitate subsequent operations at wafer sawing, back grinding, scribing and breaking, wafer probing, die attach, and various pick and place operations, typical semiconductor procedures include the mounting of wafers on a sheet of adhesive tape material (blue tape is common) that is held in place by an outer metal ring assembly. As the adhesive tapes are insulative, they become highly charged whenever contact is made with the material. Charges of 20Kv and higher are typical from even just slight contact and separation (rubbing). This charging of the adhesive tape material, in turn, causes the wafer to become charged inductively. The devices on the wafer can be subsequently damaged when discharged by any large conductor such as operators, metal fixtures, robot arms, stages and chucks, etc.

The die-attach/chip-picking operations where the diced, individual chips are removed from the adhesive tape assemblies have been especially interesting from a device failure viewpoint. We have found this particular operation has resulted in perhaps more documented CDM ESD damage than any other single operation in typical semiconductor manufacturing processes. That statement is based on literally scores of case studies where this operation was analyzed…leading to documented yield improvements. And there is more to understanding the associated failure modes here than meets the eye. It has been determined that at least 7 different failure mechanisms to chips can exist here as we will describe in detail...

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