Kester - Defect Minimization Methods for a No-Clean SMT Process

Our thanks to Kester for allowing us to reprint the following article.
By Kurt Rajewski, Assistant Manager - Market Technology, Kester

Key competitive advantages can be obtained through the minimization of process defects and disruptions. In today's electronic manufacturing processes there are many variables to optimize. By gaining an understanding of what the defects are, and where they come from, is a key step in the process towards defect free/six sigma manufacturing. In the last decade, Surface Mount Technology processes have been slowly converting towards the No-Clean philosophy. This new trend has spawned new processing issues which need to be addressed. This paper will investigate solutions to current problems in the processing of No-Clean SMT processes. These solutions will be critical in the development of successful processes in the electronics industry in the years ahead.


Introduction:


This paper will discuss commonly experienced defects associated with No-Clean surface mount processes and propose methods to solve these issues. Much of the discussion can be applied to any surface mount process (i.e. water soluble, RMA, or No-Clean), but some are directly associated with No-Clean processes. Some of these defects are due to inefficient reflow profiles - examples of these defects would include cold solder joints, non-wetting, solder balling, and tombstoning.


Other defects can be primarily attributed to the solder paste printing process - these would include insufficient solder joints, bridging, and solder balling; while others can be attributed to miscellaneous process variables - these would include skewed components, solder beading, and solder balling...


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